![]() ![]() The block containing the cnt/counter variable and signal (integer): receive_counter : process (reset, receive_add, receive_rst) What I gather from this is that somehow Synplify fails to infer that an asynchronous reset is being used, though I get the first error for other lines as well without the warning provided for the same line. The second line is a warning (CL116), but is not found in the manual and google comes up empty as well. The first error is CL126 and is described in the manual as 'The HDL code contained an incomplete description of an asynchronous load on a sequential element.' An asynchronous reset may be missing from the sensitivity list. ![]() Input data for signal counter(31 downto 0) contains references to signal edges. While trying to compile and synthesise my VHDL design using Synplify Pro (Lattice edition), I get the following errors and warnings: Asynchronous load of non-constant data for counter(0) is not supported ![]()
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